Typically in semiconductor device applications, numerous devices are packed into a small area of a semiconductor substrate to create an integrated circuit. Generally, these devices need to be electrically isolated from one another to avoid problems among the devices. Accordingly, electrical isolation is an important part of semiconductor device design to prevent unwanted electrical coupling between adjacent components and devices. This is particularly true for high density memory, including but not limited to, flash memory.
Shallow trench isolation (STI) is one known conventional isolation method and provides very good device-to-device isolation. An STI process generally includes the following steps. First, a trench is formed in a semiconductor substrate using wet or dry etching with a mask. Then, an insulating layer is deposited on the entire surface of the semiconductor substrate to fill the trench. Finally, chemical mechanical polishing (CMP) is used to planarize the insulating layer. The insulating layer remaining in the trench acts as an STI region for providing isolation among devices in the substrate. Additionally, a nitride or oxidation layer may be formed on the sidewalls and bottom of the trench before depositing the insulating layer.
As semiconductor devices get smaller and more complex, and as packing density increases, the width of the STI regions also decreases. In addition, for certain types of electronic devices, a deeper isolation trench is desired. When filling an isolation trench with a high-density plasma oxide having good filling capability, voids or seams may exist in the isolation regions. This void formation problem occurs in the formation of traditional isolation trenches as well as the so called goal-post type shaped trenches. These void defects cause electrical isolation between the devices to be reduced. Poor isolation can lead to such problems as short circuits and can further reduce the lifetime of one or more circuits formed on a substrate.
FIGS. 1A and 1B illustrate isolation trenches 11 formed in a semiconductor substrate 10 in accordance with the prior art. Before forming the isolation trenches 11, other layers may be blanket deposited over the semiconductor substrate 10; for example, FIGS. 1A & 1B illustrate layers later used to form gate structures, including an oxide layer 12, a polysilicon layer 14, and a nitride layer 16. After the trenches 11 are formed through layers 12, 14, 16 and into substrate 10, an insulating layer 20 is deposited over the layers 12, 14, 16 and semiconductor substrate 10 to fill the trenches 11. The insulating layer 20 can be deposited using high density plasma (HDP) or high-density plasma chemical vapor deposition (HPDCVD) techniques. Due to the shape of the trenches 11, the HDP or HPDCVD process tends to leave void regions 22 or seams 24 in the insulating layer 20, as shown in FIGS. 1A and 1B, respectively.
Voids 22 occur because the insulating layer 20 deposited on the sidewalls at the top of a trench 11 grows thicker than the portion closer to the bottom of the trench 11. Therefore, the opening at the top of the trench 11 becomes closed-off before the entire volume of the trench 11 can be filled causing the formation of the void region 22. The void region 22 diminishes the isolation properties of the filled trench 11. Moreover, the filling material, typically an oxide, tends to be non-conformal and thus, fails to conform to the profile of the surface ideally.
Seams 24 occur where the opposing faces of the inward growing insulating layer 20 within a trench 11 are joined together. While seam 24, in and of itself, does no harm in the structure, if the structure of FIG. 1B is exposed to etching steps during subsequent processing, the portion of insulating layer 20 adjacent seam 24 may be more sensitive to etching than the rest of material 20, which will reduce the isolation properties of the filled trench 11 in a similar manner to that of void 22.
Another problem with voids 22 and seams 24 are that they can be exposed during subsequent process steps and either trap contamination, and/or cause surface roughness. Consequently, films deposited after the roughness (voids 22 and seams 24) has been exposed will not form a consistent, flat layer, but will instead follow the contours of the void or seam below. The inconsistent, resulting film can lead to subsequent breaks in the film. These breaks, if patterned and etched later, will make it increasingly hard to remove the resulting film layer from the void, and thus can electrically short together two areas that are intended to be isolated.
Accordingly, there is a need and desire for a method of filling trench isolation regions that achieves high quality isolation, but also reduces the formation of voids and seams in the insulating material. An improved trench isolation region is also desired.